In the field of digital signalling, the presence of noise on a voltage supply line can affect the timing of signal transitions (i.e. transitions from a ‘low’ or ‘0’ state to a ‘high’ or ‘1’ state and vice versa), thereby advancing or delaying such transitions relative to an intended or expected timing position.
FIG. 1 illustrates an example of a typical interface driver 100 for transmitting digital signals across a plurality of signal lines. The interface driver 100 is arranged to receive a clock signal (Clk) 110. The interface driver 100 transmits the clock signal 110 as a data strobe signal (referred to as a DQS signal in terms of dual data rate (DDR) technology) 115, which is used at a receiving interface (not shown) as a timing reference signal with reference to which data signals are sampled. For example, in a case of a dual data rate (DDR) interface, whereby data signals are transmitted on rising and falling edges of a timing signal, a receiving interface samples data signals after a calibrated delay following each rising and falling edge of such a timing reference signal. Such a calibrated delay may comprise a duration equal to, say, a quarter cycle of the DQS signal 115 (which for the illustrated example equals a quarter cycle of the clock signal 110). The interface driver 100 is further arranged to provide the clock signal 110 to output latches 120, each output latch 120 being arranged to receive one of a set of data states 130 to be output, and upon receipt of a rising or falling edge of the received clock signal to output the received data states 130 as a set of data signals 140.
For high speed interfaces, such as by way of example a double data rate (DDR) interface that is typically used for providing an interface for synchronous dynamic random access memory (SDRAM), the high data rate means that the interval between rising and falling edges of the timing signal, and thus the interval within which a receiving interface has to sample a set data signals, is very short. Consequently, in order to ensure that a receiving interface has sufficient time to sample a current set of transmitted data signals before they are overwritten by a subsequently transmitted set of data signals, it is known for the interface driver 100 to delay (relative to the rising or falling edges of the received clock signal) the transition between successive data states of data signals being transmitted. The delayed transitions may be applied a short time before they are due to be sampled by a receiving interface. In this manner, the overwriting of a set of data signals by the next set of data signals is delayed for as long as possible, in order to provide the receiving interface with as much time as possible to sample the data signals. In this manner, a highest possible data rate may be achieved. Accordingly, the interface driver 100 of FIG. 1 is arranged to provide the clock signal 110 to the output latches 120 via a delay circuit 160, which for the illustrated example comprises a plurality of delay elements connected in series. In this manner, the output latches 120 receive a delayed version 150 of the clock signal 110.
FIG. 2 illustrates an example of a timing diagram 200 for the interface driver 100 of FIG. 1. The clock signal 110 of FIG. 1 is illustrated first, with one clock cycle thereof being illustrated generally at 215. A delayed clock signal 150 provided by the delay circuit 160 of FIG. 1 is illustrated, the delayed clock signal 150 comprising a delay that is relative to the clock signal 150 of approximately a quarter cycle, as illustrated generally at 250. The timings at which transitions for sequential sets of transmitted data signals are completed are illustrated generally at 220. As can be seen, there is a delay, illustrated generally at 225, between the rising and falling edges of the delayed clock signal 150, provided to the output latches 120 and thereby the completion of the transitions. Such a delay 225 is a result of a time period that is required to drive a transition from one state to another, and for the data signal to subsequently settle following such a transition. Accordingly, such a delay 225 is required to be taken into consideration when designing the delay circuit 160, in order to ensure the transitions are completed before a receiving interface attempts to sample the data signals 140 of FIG. 1. The time taken for driving a transition from one state to another, and thus the delay 225 in completing a transition, is affected by noise on the voltage supply lines of the interface driver 100. Thus, noise on the supply lines is also required to be taken into consideration when implementing the delay circuit 160.
For high speed interfaces such as DDR SDRAM interfaces, where a large number of signal lines are required to be driven at high data rates, noise on the supply lines and the delays to transitions caused thereby is particularly problematic. Due to the high transition rates and speeds of such interfaces, parasitics of integrated circuit devices in which the interface drivers are implemented have a significant effect on the delay of signal transitions caused by noise on the supply lines. Furthermore, the number of transitions occurring simultaneously affects the strain put on the supply lines, and thus the amount of noise on the supply lines. Accordingly, the number of transitions occurring simultaneously further impacts the delay of signal transitions. In addition to the number of transitions affecting the noise on the supply lines, the direction and symmetry of transitions occurring simultaneously (i.e. the balance between transitions from a ‘high’ state to a ‘low’ state and transitions from a ‘low’ state to a ‘high’ state) also affects the noise on supply lines.
Furthermore, with the continued desire for lower power consumption within electronic devices, supply voltages are required to be lower, making them more susceptible to noise, whilst driver impedances are required to be higher, increasing the strain applied to the supply lines when driving transitions. For example, the specifications for the DDR3 (double data rate three) SDRAM interface specify a 1.5v supply voltage, whilst providing a 34 Ohm driver impedance. Such strict constraints applied to the driver circuit for such high speed interfaces mean that the problem of noise on the supply lines has become an even greater problem.
As the number and direction of transitions that occur simultaneously may vary significantly, the amount of supply noise caused by such transitions, and the consequential delays in such transitions completing, may also vary significantly. Consequently, in order to ensure transitions of data signals are completed before the data signals are sampled by a receiving interface, it is necessary for the delay circuit 160 of FIG. 1 to be configured such that the transitions are initiated early enough for, say, a worst case scenario. Whilst this may help to ensure transitions of data signals are completed before the data signals are sampled by a receiving interface, for the vast majority of the time transitions are initiated much sooner than actually required. As a result, the amount of time available for a receiving interface to sample a current set of transmitted data signals before they are overwritten by a subsequently transmitted set of data signals is unnecessarily reduced, thereby increasing the risk of data being overwritten before it has been sampled by the receiving interface.
A simple option for reducing the noise introduced on to supply lines, and thus the effect such noise has on the delay of signal transitions, is to reduce the parasitic inductance on supply input/output (I/O) pads of the integrated circuit devices which the interface drivers are implemented.
One way of reducing such parasitic inductance on the supply I/O pads is to use flip chip, also known as Controlled Collapse Chip Connection (C4), semiconductor devices. Such devices use solder bumps deposited on chip pads located on an upper surface of the wafer during the final wafer processing step. The ‘chips’ are then mounted by being flipped over with the solder bumps being aligned within matching pads on the external circuit. The solder is then ‘flowed’ to form an electromechanical connection. This is in contrast to the more traditional method of using wire bonding whereby the chip is mounted upright and wires are used to interconnect the chip pads to external circuit. In this manner, the inductive properties of the wire bonds are removed from the flip chip pads. However, flip chips suffer from several disadvantages. For example, flip chips require a very flat surface to be mounted on, which is not always easy to guarantee, and often difficult to maintain, as boards onto which they are mounted heat and cool. Furthermore, the short connections are very stiff, so thermal expansion of the chip must be matched to the supporting board in order to avoid the connections breaking. As a result, the use of flip chips is expensive, and, in some applications, not practical.
Another way of reducing parasitic inductance on the supply I/O pads is to increase the number of supply I/O pads. However, due to the high functionality of modern system on chips (SoCs), and the limited availability of I/O pads, this is either impractical, or impossible.